2023.04.10 │コーポレート

Logic Design (VLSI) Engineer

ポジション	Logic Design Engineer
経験年数	3+ years
勤務地	Tokyo
詳細内容	• 5+ years of Experience • Experience on logic design, lint check, synthesis, equivalence check, CDC verification • Experience on logic verification, System Verilog, UVM, Code Coverage, Assertions • Experience on chip level verification, ARM cores, Protocols ( PCIe, Ethernet, USB, DDR etc…) • Experience on following tools - Design Compiler, Formality, Conformal, Spyglass